1. Field of the Invention
The present invention relates to communication decoding devices and, more particularly, to a dynamic power adjusting device for use in a Viterbi decoder, for bit-error detection and number of bit-error estimation and dynamic power adjustment.
2. Description of the Prior Art
Combination of wireless communications and the broadband Internet is an inevitable trend of telecommunications. In the field of wireless communications, a channel is always required for data transmission. Channels as such are susceptible to interference from ambient thermal noise and, to a greater extent, electromagnetic interference, such as repeated reflection and diffraction.
In view of the aforesaid problem, the past decades saw the emergence of many communication related notions and methods, of which an important one is about forward error correction (FEC). Forward error correction is based on an error-controlling code widely used in digital communications—a sender sends out redundant bit-containing data, and a receiver detects an error by combinational features of the data received and automatically corrects the error. Among the existing forward error correction techniques, convolutional coding is a predominant one.
Convolutional coding, a major form of channel coding, is characterized by a variety of convolutional codes, depending on system specifications, for example, a wireless local area network (WLAN) and the third generation (3G) mobile communications. Convolutional coding entails the following: performing specific conversion on input digital signals by a memory-enabled sequential circuit, generating output digital signals having metric values and transmitted in a certain sequence, and correcting bit errors, caused to digital signals transmitted in a channel and corrupted as a result of noise, interference and attenuation, by a decoder at the receiving end in accordance with the metric values and sequence embodied in the signals. Among the decoders available for convolutional coding, Viterbi decoder is the best one. A typical Viterbi decoder, whose hardware requirements are relatively simple, comprises four major units, namely a branch metric unit, an add-compare-select unit, a path metric unit, and a trace back unit, in a chronological order.
A conventional Viterbi decoder is always designed to suit a specific type of convolutional code. Hence, the four major units of the conventional Viterbi decoder, namely the branch metric unit, the add-compare-select unit, the path metric unit, and the trace back unit, are designed in light of the known parameters of the intended convolutional code, such as constraint length and generator polynomials. Referring to FIG. 1, which is a block diagram of the structure of a conventional Viterbi decoder 1. A branch matrix unit 10 receives a plurality of data to be decoded. Computation is performed on the data received and to be decoded, using a state matrix corresponding to a convolutional code. A branch metric value is outputted to an add-compare-select unit 20. An add-compare-select operation is performed on the branch metric value and a path matrix previously stored in a path metric unit 30 with a view to generating a new path matrix. The new path matrix is sent to the path metric unit 30 for storage. A trace back unit 40 selects a small path matrix in accordance with a value generated as a result of the operation performed by the add-compare-select unit 20. Trace back computation is performed, so as to output a decoded single bit.
Referring to FIGS. 2A and 2B, which are schematic views showing the operation of a conventional Viterbi decoder, where X(D) denotes a source signal, the source signal X(D) is encoded by a coding polynomial G(D). As shown in FIG. 2A, with the coding polynomial G(D)=[1+D2+D3+D5+D61+D+D2+D4+D61+D+D2+D3+D6], the source signal X(D) is encoded to yield an encoded signal Y(D). Then, the encoded signal Y(D) passes through a noisy channel and produces an erroneous signal E(D). Finally, both the encoded signal Y(D) and the erroneous signal E(D) undergo Viterbi decoding to recover the delayed source signal.
Nevertheless, a conventional Viterbi decoder consumes the same amount of power, whether bit error-containing signals are zero biased or not. Hence, a scarce-state-transition (SST) Viterbi decoder was developed with a view to solving the aforesaid problem. As shown in FIG. 3, a SST Viterbi decoder 200 differs from a conventional decoder 1 in that the SST Viterbi decoder 200 comprises a front-end processing unit 4 and a back-end processing unit 5. The front-end processing unit 4 generates a bit error-containing signal after receiving a plurality of data to be decoded, reduces variation of signals entering the conventional Viterbi decoder 1 because of zero biased bit error-containing signals, reduces power consumed for variation of signals of an inbuilt processing unit, sends the bit error-containing signal to the conventional Viterbi decoder 1 for decoding. Eventually, the back-end processing unit 5 outputs a decoded signal.
Referring to FIG. 4, which is a schematic view showing the operation of a SST Viterbi decoder. As shown in the drawing, the source signal X(D) is encoded by a coding polynomial G(D) so as to generate an encoded signal Y(D), and then the encoded signal Y(D) passes through a noisy channel so as to generate an erroneous signal E(D). Both the encoded signal Y(D) and the erroneous signal E(D) are transformed by an anti-matrix G−1(D) of the front-end processing unit 4 so as to obtain a polynomial X(D)+E(D)G−1(D) whereby the bit error-containing signal is zero biased. Then, the polynomial X(D)+E(D)G−1(D) processed signal is sent to the back-end processing unit 5 to generate (X(D)+A(D))Dvd after a delay time Dvd. The polynomial X(D)+E(D)G−1(D) is transformed by a matrix G(D) so as to obtain Y(D)+A(D)G(D), where A(D) equals E(D)G−1(D). An exclusive OR (XOR) gate operation is performed between Y(D)+A(D)G(D) and the Y(D)+E(D) generated because of encoding and passing through the noisy channel, so as to generate an erroneous signal, as expressed in A(D)G(D)+E(D), and send the erroneous signal to the conventional Viterbi decoder. Then, the erroneous signal enters the back-end processing unit 5 and undergoes an operation of (X(D)+A(D))Dvd as a result of transformation by the anti-matrix G−1(D), so as to generate a delayed source signal X(D)Dvd.
With a zero biased bit error-containing signal, the SST Viterbi decoder 200 reduces variation of signals entering the conventional Viterbi decoder 1. However, the SST Viterbi decoder 200 reduces variation of processing-related, rather than clock-related, signals, and thus the reduction of power consumption is quite limited. Besides, it is a flip flop and a clock buffer tree which account for most of the power consumed by the conventional Viterbi decoder. Hence, strictly speaking, the SST Viterbi decoder 200 fails to achieve power saving through a zero biased bit error-containing signal.
Accordingly, an issue calling for urgent solution involves reducing power consumption dynamically during a communication decoding process.